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MC44871
Advance Information
PLL Tuning Circuit with DC-DC Converter, I2C Bus and ADC
The MC44871 is a tuning circuit for TV, VCR and Multimedia tuner applications. This device contains on one chip all the functions required for PLL control of a VCO. This integrated circuit also contains a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44871 has an integrated dc/dc converter to generate the 30 V supply voltage for the tuning amplifier on the chip. A tuner using the MC44871 does not require an external 30 V supply. The MC44871 is controlled by a I2C bus, and has a chip address function. The MC44871 data format is the same as the MC44818. The MC44871 is manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
PLL TUNING CIRCUIT
WITH HIGH SPEED I2C BUS AND 30 V TUNING SUPPLY
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * *
The Pin Called VCC2 for the MC44818 is Now Called CP (Charge Pump). This Pin is the Output of the DC/DC Converter; a 1.0 nF Capacitor Replaces the Need for an External 30 V Supply High Speed I2C Bus (up to 800 kHz) I2C Bus Read Mode for Lock Detector and AFC Level HF Input is Balanced MC44871 has Three PNP High Current (30 mA) Band Buffers (B0, B1, B2) and One NPN Low Current (5.0 mA) Band Buffer (B4) VCC Internally Supplies PNP Band Buffers The Tuning Voltage is Generated Through an External Pull-Up Resistor (750 k) Less Phase Comparator Output Current Single 5.0 V Supply Operation
VTUN
16
1
DTB SUFFIX PLASTIC PACKAGE CASE 948F (TSSOP-16)
PIN CONNECTIONS (16 Pin TSSOP)
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Amp In Xtal SCL SDA ADD VCC ADC B4
MOSAIC is a trademark of Motorola, Inc.
CP HF1 HF2 Gnd B2 B1
ORDERING INFORMATION
Device MC44871DTB Operating Temperature Range TA = -20 to +85C Package TSSOP-16
B0
(Top View)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Motorola, Inc. 1998
Rev 1
MOTOROLA ANALOG IC DEVICE DATA
1
MC44871
Figure 1. Representative Block Diagram
VTUN C4 R1 C1 VCC 11 CP 2 DC/DC Converter 9 6 7 8 Bands Out VTUN 1 16 Vref Operational Amplifier T13 5 T14 T10, T11 P-On Reset DTB2 POR SDA SCL ADD 13 14 12 I2C Bus Receiver CLO Data RL DTF 4 Shift Register 15 Bit 15 Latches A 3.2 or 4.0 MHz 15 Xtal Osc ADC ADC 10 Preamp HF1 3 HF2 4 /8 Prescaler Program Divider 15 Bit Fout Latch Control Latches B TDI Ref Divider 6 Latches Fout Phase Comp Amp In C2 C3 R2
5.0 V Fout Fref
B4 Test Logic DTB1
B2 B1 Buffers Latches
B0
Gnd
Fref
512/1024
DTS This device contains 3,204 active transistors. Approximate values of the external components for generation of the tuning voltage are: C1 = 1.0 nF Charge Pump filter capacitor R1 = 750 k (560 k minimum) Pull-up resistor C4 = 330 pF VTUN filter capacitor C2 = 47 nF, C3 = 22 nF, R2 = 39 k Loop filter These component values depend on the application.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44871
MAXIMUM RATINGS (Maximum ratings are those values beyond which permanent damage to the device may occur. Exposure to those limits may also affect device reliability; TA = 25C, unless otherwise noted.)
Rating Power Supply Voltage (VCC) Storage Temperature Operating Temperature Range Operational Amplifier Output Voltage RF Input Level 80 MHz to 1.3 GHz NPN Band Buffer "Off" Voltage NPN Band Buffer "On" Current PNP Band Buffer "Off" Voltage PNP Band Buffer "On" Current PNP Band Buffer - Short Circuit Duration (Note 1) Band Buffer Operation at 40 mA all PNP Buffers "On" Pin 11 - - 1 3, 4 9 9 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 Value 6.0 -65 to +150 -20 to +85 40 1.5 10 15 6.0 50 Continuous 10 Unit V C C V Vrms V mA V mA - s
NOTES: 1. At VCC = 5.0 V and TA = -20 to +80C one buffer "On" only. 2. ESD data available upon request.
ELECTRICAL CHARACTERISTICS (Parameter Type: A-100% Tested, B-100% Correlation Tested, C-Characterized on
Samples, D-Design Parameter, VCC = 5.0 V, TA = 25C, unless otherwise specified, 750 k pull-up resistor between CP [Pin2] and VTUN [Pin 1].) Characteristic VCC Supply Voltage Range VCC Supply Current (All Buffers "Off") One Buffer "On" when Open One Buffer "On" at 40 mA PNP Band Buffer B0, B1, B2 Leakage Current when "Off" PNP Band Buffer B0, B1, B2 Saturation Voltage when "On" at 30 mA NPN Band Buffer B4 Leakage Current when "Off" NPN Band Buffer "Off" Voltage NPN Band Buffer B4 Saturation Voltage when "On" at 1.0 A NPN Band Buffer B4 Voltage when "On" @ 5.0 mA Reference Oscillator Frequency Range Phase Comparator 3-State Current Phase Comparator Output Current - High Value Phase Comparator Output Current - Low Value DC-DC Converter Output Voltage, Sourcing 50 A DC-DC Converter Maximum Current, Output Short Circuited DC-DC Converter setting time from VCC >4.5 V to DC-DC Converter Voltage > 28 V @ Load = 750 k/1.0 nF Operational Amplifier Internal Reference Voltage (Vref) Operational Amplifier Input Current Operational Amplifier DC Open Loop Gain Operational Amplifier Gain Bandwidth Product (CL = 1.0 nF) Operational Amplifier Low Output Voltage, Sinking 50 A Oscillator - Negative Resistance Pin 11 11 6, 7, 8 6, 7, 8 9 9 9 9 15 16 16 16 2 2 2 - 16 - - 16 15 Min 4.5 - - - - - - 0 - - 3.15 -15 12 2.0 28 - - 1.3 -15 100 0.3 - 1.0 Typ 5.0 35 40 80 0.01 200 0.01 - 50 1.2 3.2 0 20 6.0 31 200 - 1.9 0 300 - 0.2 - Max 5.5 45 50 90 1.0 500 1.0 5.5 100 1.6 4.05 15 28 10 34.5 350 25 2.5 15 - - 0.4 - Unit V mA A A mV A V mV V MHz nA A A V A ms V nA - MHz V k Type A A B B A B A D A A D A A A A A C A A A D D D
MOTOROLA ANALOG IC DEVICE DATA
3
MC44871
PIN FUNCTION DESCRIPTION (see Figure 1)
Pin 1 2 3, 4 5 6, 7, 8 9 10 11 12 13 14 15 16 Symbol VTUN CP HF1, HF2 Gnd B2, B1, B0 B4 ADC VCC ADD SDA SCL Xtal Amp In Description Operational amplifier output which provides the tuning voltage DC-DC Converter output (Charge Pump) Symmetrical HF inputs Ground PNP Band Buffer outputs NPN Band Buffer output Three bit ADC for Automatic Frequency Tuning, readable through the bus Positive supply of the circuit (5.0 V) Chip address function I2C bus Data Input/Output I2C bus Clock Crystal Oscillator (3.2 MHz or 4.0 MHz) Operational amplifier input
HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (VCC = 5.0 V, TA = 25C.) (See Figure 2.)
Characteristics DC Bias (Internal) 80-150 MHz 150-600 MHz 600-950 MHz 950-1300 MHz Pin 3, 4 3, 4 3, 4 3, 4 3, 4 Min - 10 5.0 10 50 Typ 1.6 - - - - Max - 315 315 315 315 Unit V mVrms mVrms mVrms mVrms Type A C C C C
Figure 2. HF Sensitivity Test Circuit
Bus Bus Controller
Figure 3. Typical HF Sensitivity Performance (VCC = 5.0 V, Temperature = 25C)
10 0 Guaranteed Sensitivity Performance RF LEVEL (dBm)
Counter In
VCC = 5.0 V
1.0 nF
HF Generator HF Out Gnd 50 Cable 50 1.0 nF 1.0 k 1.0 k 1.0 k
NOTE:
1. Device is in test mode. B1, B2 are "On" and B0, B4 are "Off". Sensitivity is level of HF generator on 50 load.
4
CCCCCCCC CCCCCCCC CCCCCCCC
11 4 13 14
-10 -20 -30 -40 -50 -60 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz)
MC44871
B0 8 B1 7
HF1 3
Gnd 5
B2 6
B4 9
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Figure 4. Pin Circuit Schematic
50 VTUN 1 Operational amplifier output which provides the tuning voltage 20 V 20 V
10 k
2.0 k 20 V 16 Amp In Negative input of operational amplifier and phase detector charge pump output
32 V 6.0 k CP 2 Converter output (Charge Pump) 1.5 k 20 V 20 V 1 2 5.0 V 5.0 V VCC 96 k 1/2 VCC 2.0 k HF1 3 2.0 k Inputs to presealer VCC 96 k 1/2 VCC 96 k 132 k 96 k 1.2 ... 1.8 V
100 5.0 V 15 Xtal Crystal oscillator (3.2 MHz or 4.0 MHz)
6
5.0 V
132 k 500 14 SCL Clock input (I2C bus) 20 V
500 20 V ACK VCC 13 SDA Data input/output (I2C bus)
HF2 4
Gnd 5 Circuit ground
150 k 10 k 50 k 20 V 12 ADD Chip Address
VCC
5.0 V B2 6 20 V "On"/"Off" 5.0 V
11 VCC Positive supply of the circuit (5.0 V)
10 k PNP Band Buffers 20 V B1 7 "On"/"Off" 20 V VCC 200 20 V 9 B4 NPN Buffer 10 ADC Three bit control for AFC
B0 8
"On"/"Off" 20 V "On"/"Off"
MOTOROLA ANALOG IC DEVICE DATA
5
MC44871
HIGH SPEED I2C BUS (The circuit is controlled by a I2C bus with a Serial Data [SDA], Serial Clock [SCL], Chip Address
Control [ADD] inputs. The device I2C bus has a read mode [odd addresses] and a write mode [even addresses].
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25C, unless otherwise specified.)
Characteristic SDA/SCL Output Current at 0 V SDA/SCL Low Input Level SDA/SCL High Input Level SDA/SCL Input Current for Input Level from 0.4 V to 0.3 VCC SDA/SCL Input Level ADD Input Level SDA/SCL Capacitance SDA Low Output Level (sinking 3.0 mA) SDA Low Output Level (sinking 15 mA) Pin 13, 14 13, 14 13, 14 13, 14 13, 14 12 13, 14 13 13 Ci VIL VIH Symbol Min - - 3.0 -5.0 0 -0.01 VCC - - - Typ - - - 0 - - - 0.3 - Max 10 1.5 - 5.0 VCC + 0.3 1.1 VCC 10 1.0 1.5 pF V V Unit A V V A V Type A B B C D D C A C
TIMING CHARACTERISTICS
Characteristic Bus Clock Frequency Bus Free Time Between Stop and Start Setup Time for Start Conditions Hold Time for Start Condition Data Setup Time Data Hold Time Setup Time for Stop Condition Hold time for Stop Condition Acknowledge Propagation Delay SDA Fall Time at 3.0 mA sink I and 130 pF Load SDA Fall Time at 3.0 mA sink I and 400 pF Load SDA/SCL Rise Time SCL Fall Time Pulse Width of Spikes Suppressed by the Input Filter 13 13 13, 14 13, 14 13,14 Tsp Pin 14 - - - - - - - Tbuf Tsu;sta Thd;sta Tsu;dat Thd;dat Tsu;sto Thd;sto Tack;low Symbol Min 0 200 500 500 0 0 500 500 - - - - - - Typ - - - - - - - - - - - - - - Max 800 - - - - - - - 300 50 80 300 300 50 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns Type C C C C C C C C C C C C C C
Timings Definition
Tbuf Start Stop Stop Start Chip address
ACK
SDA
SDA
SDA
SCL
Tsu;sta
SCL
Thd;sto
SCL
Tsu;sto Thd;sta Tsu;dat Thd;dat Tack:low
Levels Definition
VCC VIH Not Defined VIL 0V
6
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Figure 5. High Speed I2C Compatible Bus Data Format
1 2 3 4 5 6 7 8 9 10 18 19
SCL
SDA
STA
Chip Address ($C2) ACK
First Byte ACK 2 or 4 Data Bytes ACK
Stop
I2C Write Mode Format and Bus Receiver The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA 4_STA CA CA CA CA CO FM CO FM BA FL BA FL FM FL CO BA STO STO STO STO
ignored. If five or more data bytes are received, the fifth and following ones are ignored, and the last acknowledge pulse is sent at the end of the fourth data byte. The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. If the function bit is logic "1", the two following bytes contain control and band information. The first data byte, after the chip address, may be byte CO or byte FM. The two bytes of frequency information are preceeded by a logic "0". Chip Address Even addresses are for write mode, and odd addresses are for read mode. Chip address is programmable by Pin 12 (ADD).
ADD Pin 12 -0.01 VCC to 0.1 VCC 0.2 VCC to 0.3 VCC (or Open) 0.4 VCC to 0.7 VCC 0.8 VCC to 1.1 VCC Address (HEX.) C0/C1 C2/C3 C4/C5 C6/C7
STA = Start Condition CA = Chip Address Byte CO = Control Information BA = Band Information FM = Frequency Information with MSB FL = Frequency Information with LSB STO = Stop Condition Figure 5 shows the five bytes of information that are needed for circuit operation: the chip address, two bytes of control and information, and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received, the third one is
MOTOROLA ANALOG IC DEVICE DATA
7
MC44871
The Two Permissible Protocols with Five Bytes
CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK
CO_Control Information BA_Band Information
FM_Frequency Information FL_Frequency Information
CA_Chip Address
FM_Frequency Information FL_Frequency Information
CO_Control Information BA_Band Information
I2C Read Mode Format The incoming information consists of the chip address byte in read mode (odd address). The device then answers with an acknowledge followed by a byte containing lock and ADC information. There is no ACK pulse sent after this byte. I2C Read Format
CA_Chip Address 1 1 0
ADC_LO
Definition of the Bits for Test and Features Bits B0, B1, B2: Control the PNP Band Buffers
B0, B1, B2 = 0 =1 Buffer is "Off", Output Low Buffer is "On", Output High
Bit B4: Controls the NPN Band Buffer
B4 = 0 =1 Buffer is "Off", Output High Buffer is "On", Output Low
Bit T8: Controls the Operational Amplifier Output
T8 T8 = 0 =1 Operation Operational Amplifier Normal Operation Output State of Operational Amplifier Switched Off Output Pulls High through External Resistor
8
EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE
1 T14 X T13 X T12 B4 T11 X T10 B2 T9 T8 ACK ACK X B1 B0 0 N14 N6 N13 N5 N12 N4 N11 N3 N10 N2 N9 N1 N8 N0 ACK ACK N7 1 1 0 0 0 0/1 0/1 0 ACK
EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE
0 N14 N6 N13 N5 N12 N4 N11 N3 N10 N2 N9 N1 N8 N0 ACK ACK N7 1 T14 X T13 X T12 B4 T11 X T10 B2 T9 T8 ACK ACK X B1 B0
1_STA CA ADC_LO ADC_LO = ADC and Lock information
0
0
0/1
0/1
1
ACK
EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE
1 LO X X X AD2 AD1 AD0 (no ACK)
Bit T10, T11: Control the Reference Divider
T10 0 0 1 1 T11 0 1 0 1 512 1024 1024 512 Divider Ratio
Bit T9, T12: Control the Phase Comparator
T9 0 0 1 1 T12 0 1 0 1 Function Upper Source Only Lower Source Only Normal Operation High Impedance
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Bit T13: Switches the Band Buffer Output to Test Mode
T13 = 0 =1 Normal Operation Test Mode: Fref Out at B2 Fby2 Out at B1
OPERATING DESCRIPTION
Introduction A representative block diagram and typical system application are shown in Figures 1 and 8. A discussion of the features and function of each of the internal blocks is given. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider; this double latch scheme is needed to assure correct data transfer to the counter. The division ratio definition is given by: N = 16384 x N14 + 8192 x N13 + ... + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 256 N0 ... N14 are the different bits for frequency information. At power-on the whole bus receiver is reset and the programmable divider is set to a counting ratio of N = 256 or higher. The Prescaler The divide-by-8 prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is both phase and frequency sensitive and has very low output leakage current in the high impedance state. The Operational Amplifier The operational amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The operational amplifier output (Pin 1) needs an external 750 k pull-up resistor (560 k minimum). This minimum value is defined by the charge pump output current capability. The Oscillator The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground in series with a capacitor. The crystal operates in the series resonance mode. The voltage at Pin 15 has low amplitude and low harmonic distortion. Power Dissipation The typical power dissipation of the circuit is about 200 mW (VTUN = 15 V with external pull-up of 560 k, one buffer "On" at 30 mA). It is calculated with the following formula: PD
In the test mode, B2 and B1 have to be ON (B2=B1=1). Fref is the reference frequency. Fby2 is the output frequency of the programmable divider divided-by-2. Bit T14: Controls the Charge Pump Current
T14 = 0 =1 Pump Current 5.0 A Pump Current 20 A
Bit AD2, AD1, AD0: Indicate the ADC Pin Analog Level
ADC Input Voltage 0 to 0.18 VCC 0.18 to 0.34 VCC 0.34 to 0.5 VCC 0.5 to 0.66 VCC 0.66 to 0.82 VCC 0.82 to 1.0 VCC AD2 0 0 0 0 1 1 AD1 0 0 1 1 0 0 AD0 0 1 0 1 0 1
Bit LO: Indicates the Status of Lock Detetector
LO = 0 LO = 1 PLL Status Not Locked PLL Status Locked
Figure 6. Equivalent Circuit of the Integrated PNP Band Buffers
VCC Saturation Voltage 0.2 V Typical 0.5 V Max ISUB "On"/"Off" Out B0...B2 30 mA (40 mA at 0 to 80C)
IB
IB + ISUB = 5.5 mA Typical IB = Base Current ISUB = Substrate Current of PNP
Figure 7. Equivalent Circuit of the Integrated NPN Band Buffer
VCC = 5.0 V IB1 200 IB2 Protection 20...25 V IB3 1.2 V typ @ 5.0 mA Out B4
+
V
CC
xI
CC
)
V ) VPin2 *kWTUN 560 Out buffer
xV
TUN
V sat x I
Example: (5 x 38)
"On"/"Off" IB1 + IB2 + IB3 = 0.5 mA Typ IB = Base Current
32 15 ) 5.6 x- 105 ) (0.20 x 30) + 197 mW
x 15
MOTOROLA ANALOG IC DEVICE DATA
9
MC44871
Figure 8. Typical Tuner Application
IF UHF VHF B III Mixer Antenna Filter B. P. Filter 1.0 nF HF1 3 Fosc 1.0 nF HF2 4 VCC 11 5.0 V CP Gnd 52 1 8 B0 7 B1 6 B2 9 10 B4 Bus Rec Program Divider 14 13 12 Osc & 15 Xtal Ref Div Phase Comp ADC SCL SDA ADD External Switching
MC44871
/8
CXtal 3.2/4.0 MHz
Oscillator
Vref 16
AGC
VTUN C4 (Note 1)
C1
R1 C2
R2
C3
NOTES: 1. 330 pF minimum is required for stability. 2. Approximate values of the external components for generation of the tuning voltage are: C1 = 1.0 nF Charge Pump filter capacitor R1 = 750 k (560 k minimum) Pull-up resistor C4 = 330 pF VTUN filter capacitor C2 = 47 nF Loop Filter C3 = 22 nF Loop Filter Loop Filter R2 = 39 k These component values depend on the application.
VOLTAGE (V)
DC-DC Converter Characteristics The dc-to-dc converter block generates the 30 V supply voltage on the chip from VCC. Pin 2 only needs an external capacitor (1.0 nF) instead of an external 30 V supply. The charge pump switching frequency is taken from the oscillator. Typical charge pump output current capability at 25C is shown in Figure 9.
Figure 9. Typical Charge Pump Output Current
34 32 30 28 26 24 22 20 0 20 40 60 CURRENT (A) 80 100 120 VCC = 5.0 V VCC = 4.5 V VCC = 5.5 V
10
MOTOROLA ANALOG IC DEVICE DATA
MC44871
OUTLINE DIMENSIONS
DTB SUFFIX PLASTIC PACKAGE CASE 948F-01 (TSSOP-16) ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
MOTOROLA ANALOG IC DEVICE DATA
EEE CCC EEE CCC
M
SECTION N-N
-W-
11
MC44871
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
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MC44871/D MOTOROLA ANALOG IC DEVICE DATA

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